Over the weekend I finished most of the hardware accelerator logic, (Erick is doing the rest), and Vlad modified the software to use bit vectors rather than an array. Now it is time to figure out the details of interfacing with memory. We can use the CRC checksum accelerator as an example.. but it has more features than we need. For instance, it would be okay for the CPU to stall while waiting for the accelerator, rather than doing other work while waiting for an interrupt. Supporting these additional features will make the design more complicated; on the otherhand, trying to make something from scratch will almost certainly take longer to figure out.
Aliaa is working on the serial interface and trying to run the current software on the NIOS w/ SRAM. Vlad is improving his bit vector code to remove division where possible.
I'm not sure that we will really make the Friday deadline for full integration; but Sunday would be doable.
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